1. Field of the Invention
The present invention relates to image data processing circuits and image processing apparatus including the same.
2. Description of the Related Art
There have been known digital multifunction peripherals (also referred to as MFPs) configured to compress image data which has been obtained by scanning documents when storing the image data in a storage device and decompress and decode the compressed data into image data when printing the stored image data. The compression and decompression processes for image data are required to have processing capacities consistent with the scanning speed and the printing speed of the digital multifunction peripheral and, in many cases, these processes are performed using dedicated compression circuits and decompression circuits. However, so-called high-speed digital multifunction peripherals (hereinafter, referred to as high-speed machines) have high scanning speeds and high printing speeds and, in some cases, a single compression circuit and a single decompression circuit can not offer compression and decompression processes which follow the inputting and outputting rates. In such cases, there may be utilized a method which provides plural compression circuits and plural decompression circuits and causes image data to be divided and input to the respective compression and decompression circuits enabling parallel processes. As described above, there is known a method which provides plural compression and decompression circuits which are arranged in parallel and thus enables selecting combinations of these circuits in accordance with the input and output image data for increasing the overall efficiency of the compression and decompression processes (refer to Japanese Unexamined Patent Application No. Hei 11 (1999)-41429).
As previously described, digital multifunction peripherals include high-speed machines and other machines (referred to as medium-speed machines, in contrast with high-speed machines). For high-speed machines, a single compression circuit and a single decompression circuit can not perform compression/decompression processes followable to the inputting/outputting speeds. The medium-speed machines do not require the compression and decompression circuits to have processing speeds as high as those for high-speed machines, thereby allowing a single compression circuit and a single decompression circuit to realize processes. Medium-speed machines allow a pair of compression/decompression circuits to compress scanned data and decompress to-be printed data while high-speed machines require plural compression and decompression circuits in order to offer image data processes which can follow the inputting and outputting. Further, the image data processing capacity is determined by the data transferring capacity for transferring image data obtained by scanning documents to the compression circuit and by the data transferring capacity for transferring image data decompressed by the decompression circuit to or from a memory. Image data transferred through the aforementioned portions is not compressed and thus has a large data quantity, which tends to restrict the processing capacity. This tends to restrict the processing capacity more significantly when the number of bits per pixel is increased, when the resolution is increased or when the inputting and outputting rates are increased for increasing the image quality.
In many cases, these image-compression/decompression circuits are realized using ASICs (or Application Specific ICs) in order to satisfy requirements in the performance and the cost. However, the compression and decompression circuits have large circuit scales and, if the compression and decompression circuits are configured to be arranged in parallel for high-speed machines, the ASIC will have surplus performance and involves a high cost, while if the ASIC is optimized for medium-speed machines, the ASIC will not satisfy the performance requirement of high-speed machines. However, in view of the cost and the number of developing processes, ASICs configured to be usable for both high-speed machines and medium-speed machines are preferable.
On the other hand, as the compression and decompression processes in the digital multifunction peripherals, there has been a need for other processes such as decompressing data which has been compressed and stored in a storage device, then performing image processing, compressing it again and then transmitting it to the outside through a network, etc., in addition to the compression of the aforementioned scanned data and the decompression of to-be printed data. Then, it is desirable that such processes are performed in parallel with the processes for scanned data and to-be printed data. In order to cope with such parallel processes, it is necessary that the compression/decompression circuits are arranged in parallel with one another such that the numbers of the compression/decompression circuits correspond to the number of required processes.